Responsibility 1. In charge of designing and verifying Hardware module 2. Assistant for leading the ASIC project on high level design and verification activities 3. Communication with Japan peer in project level n Requirement 1. experience in SW design and verification, language skill should C,C++. (Excellent fresh graduates are also welcomed.) 2. Needs to have HW design knowledge and experience, Needs Verilog or VHDL language skill. If have experience of SoC development is better. 3. Fluent English skill (in working environment, Fluent in listening, reading, writing). Fluent JP skill is better.
4.Work in WX
接受应届电子半导体专业硕士人员