Job Description:
As an intern for Physical IP Development and Evaluation Program, you will join a talented team to develop and evaluate Physical IP and related supportive materials. Your responsibilities will be related, but not limited to:
Setup spice simulation environment and execute the simulation.
Check / summarize the simulation data
Perform PDK data comparison between different version, different fab with same process node, or different process node from same fab, etc.
Perform performance analysis for SRAM bitcell
Automate the comparison flow with script, perl, etc.
Qualifications needed:
Micro-Electronic or Semiconductor related background within master program, or 3rd year degree within bachelor program;
Fair knowledge of IC design flow.
Fast learner
Nice communication, good positive and self-motivated personalities
Sufficient English reading and writing skills;
Nice to have:
Good Verilog RTL coding skills;
Familiar with Synopsys/Cadence EDA tools;
Familiar with C/C++.