Design Verification Intern

Responsibility: ·  Develop micro-architecture specification for GPU blocks. ·  Develop RTL code for GPU blocks in Verilog HDL. ·  Responsible for Front-End chip implementation including design, implementation and execution of  the flow that starts with RTL code and ends with the delivery of a netlist package ready for physical design. ·   Responsible for ASIC design methodology and flow development, interfacing with EDA vendors on technology. Requirement: ·   Master or above degree. ·   Major in Micro-E or related, Electronic Engineer, Computer Science, Mathematics. Communication. ·   Familiar with Verilog HDL coding and ASIC Frond-End implementation flow. ·   Familiar with unix/linux and scripts (tcl, perl, python etc.). ·   Strong task-based organization skills. ·   Computer architecture and computer arithmetic (a plus). ·   Computer graphic basic knowledge (a plus). ·   Experience with Database technologies and database-driven custom web application development (a plus). ·   Proficient English and Mandarin (listening, writing and speaking). ·   Have project experience during university education. ·   Strong passion in achievement and career development. ·   A self-motivated team player.