数字后端实习生 PD and Power Reductions Intern

Key Responsibilities 1. Power reduction Methodology in Digital physical design

2. Floorplan, Place and Route , Timing/DRC/IR/EM checking/fixing

3. flows/tools methodology

Skills and Experience Requirements 1. Understanding basic ASIC design flow

2. Bachelor and above in microelectronics, or related area

3. With experience on Verilog or System Verilog

4. Sufficient knowledge in Perl/Python/Ruby/Java/C/C++ is a strong plus

 5. Nice to have development experience under Linux, knowledge of Shell/Make/VIM/