Power methodology/analysis team is responsible for researching power expenditures and workload efficiency to identify architectural, micro-architectural strategies to improve power efficiency of the next generation GPU and TEGRA chips.
What you’ll be doing:
· Develop the power flow to automate the power expenditures measurement.
· Evaluate new low-power technologies and improve chip power efficiency on architectural level.
· Support GPU/TEGRA RTL designers using the power flow and improve their power efficiency on micro-arch level.
· Understand and perform block level and chip-level power analysis.
What we need to see:
· MSEE/MSCS with experiences on ASIC related areas.
· Familiar with advanced low power techniques and high speed clocking desired.
· Experience in low power ASIC design/verification.
· Programming languages: Strong Verilog (or VHDL), Strong scripting languages skills, preferred Perl, Tcl/python/C ++ is a plus.
· Tool Familiarity: VCS simulation tool is must, PTPX, Synopsys Design Compiler, Power Artist is a plus.