esponsibilities:
SoC level DFT architecture definition.
Cutting-edge test strategies study and implementation.
Cutting-edge IP study (both DFT and non-DFT designs ) and test plan development.
ATE/SLT yield analysis and root cause.
Block and SoC level DFT implementation, including SCAN, MBIST, RTL integration, STA, etc.
Plan/Implement block/chip level DFT RTL designs basing on FloorPlan.
MBIST chip level plan, RTL insertion, verification and pattern generation.
Develop high coverage and cost effective test patterns, and take part in ATE bring-up.
Co-work with Front End and PD for synthesis optimization and smooth timing signoff.
Requirements:
Solid background on process, device or ASIC design.
Proven knowledge and expertise on two or more fields of SCAN, MBIST, RTL design, STA and DV.
Experience in Synthesis, formal/LEC, or power analysis will be a plus.
Good command of two or more standard EDA tools, and has solid knowledge on state of the art test strategies.
Strong programming and scripting skills in Perl or Tcl.
Good communication skills (both English and Mandarin) and self-driven, willing to learn/share.