Responsibilities:

1. Implement SOC DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro test logic.
2. Perform verification on all DFT structures
3. Generate DFT related timing constraints and work with PD team for timing closure
4. Generate and verify DFT structural patterns and functional patterns
5. Participate in ATE bring-up and debug the DFT patterns on ATE
6. Design and implement other DFX (debug, characterization, yield etc) logics