Responsibilities 1.Responsible for all the aspects of the ASIC front end design, including the micro- architecture, RTL, synthesis, logic and timing verification; 2.Document, execute the plan, and deliver fully verified, high performance, area and power efficient design to achieve the targets and specifications; 3.Work with the verification team, guide and review the verification plan; 4.Participate in post silicon bring-up and validation.

Qualifications 1.1～5 years of complex high-speed digital IC design experience with all stages in the ASIC design flow including emulation, prototyping, DFT, Synthesis, timing analysis, floorplanning, ECO, bringup & lab debug, and ATE test development; 2.Bachelor’s degree in Electrical Engineering or Computer Engineer or related field required; MS or Ph.D. degree a plus; 3.Experience with standard EDA tools from Synopsys or Cadence; 4.Strong working knowledge of languages relevant to the ASIC development process including Verilog, Unix/Perl Scripting or Python, and C/C++; 5.Excellent knowledge of ARM subsystem, PCIe and industry standard peripherals including I2C, UART, SPI; 6.Experiences with complex networking ASIC design and knowledge with networking protocols and RFCs are big plusses. Compensations We offer very competitive salary, significant stock equity, and generous benefits plan.