The candidate should have good understanding on ASIC/SOC design flow and must be proficient in two or more of the following skill sets:
1. RTL(verilog) coding and style checking
2. scripts based on makefile, perl, TCL or csh/tcsh
3. clock-domain-cross checking
4. dynamic logic simulation or post-layout simulation
5. logic synthesis or physical Synthesis
6. static timing analysis
7. logic equivalency checking
8. design for test, design for debug or design for power
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English,
imaginative thinking and sophisticated analytical techniques, self-driven for quality and timely result, capability to solve complex problems and makes some modifications to standard methods and decision-making on important technical areas.
The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC project.
The role will include working on the following tasks from time to time: specification, top level SOC design tasks, synthesis, timing closure, etc.