Intel Labs China is looking for passionate and creative interns specializing in RISC-V based SoC interconnect design and explore. Below are the potential directions you might be involved in during your internship: 1. Design and develop novel coherent interconnect topologies and protocols tailored for RISC-V-based multi-core systems, considering diverse application domains and use cases 2. Evaluate and optimize interconnect designs through simulation, modeling, and performance analysis, considering both functional and non-functional requirements. 3. Collaborate with cross-functional teams including architects, designers, and verification engineers to integrate and validate interconnect solutions within RISC-V SoCs. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: * Currently enrolled in a master's or PHD's program with a major in fields such as Electrical Engineering, Computer Engineering, or related areas. * Strong interest in SoC chip architecture design, advanced package design, familiarity with relevant hardware description languages, and design tools is a plus. * Team collaboration skills, innovative thinking, and problem-solving abilities are essential.