THE ROLE:

College intern for RTG SOC DFT scan domain related work of AMD dGPU projects in our Shanghai R&D Center (SRDC). The intern position will mainly focus on the tile level scan insertion and ATPG.

 

KEY RESPONSIBILITIES:

Co-work with cross team to finish tile scan insertion and ATPG in each milestone.

Work with other scan team engineers to do tile level scan pattern generation and simulation

Develop automation script to improve the work efficiency

 

REQUIRED SKILLS:

Bachelor or MS in Electrical Engineering, Micro-Electrical.

Highly motivated, innovative individual with a keen interest in finding and resolving silicon/platform issues

Basic knowledge of DFT and scan domain would be a plus

Script language (Perl/TCL) skills would be a big plus

Good written and oral English skills

 

EDUCATION:

Recent college students with bachelor or master’s degree of ME/EE or relative majors

 

LOCATION:

Shanghai