Responsibilities:

1.Create and maintain RTL integration of system level components

2.Write verification plans for system level IPs and systems

3.Develop verification environments for IP and systems using C, verilog, SystemVerilog, etc

4.Work closely with US team members

Requirements:

1.MS/PhD in Electrical/Computer Engineering

2.Fluency in English to speak without support from others directly with US team members

3.Strong coding skills - using languages: Verilog, SystemVerilog, Perl, assembly, C++, C, Linux

4.Great debugging and problem isolation skills

5.Strong knowledge of AXI, AHB, APB interconnect

6.Strong knowledge of Computer architecture, instruction sets, memory subsystems

7.Strong experience with Implementing RTL logic designs